In the design of integrated circuits, particularly digital circuits, standard cells having fixed functions are widely used. Standard cells are typically pre-designed and stored in cell libraries. During an integrated circuit design process, the standard cells are retrieved from the cell libraries and placed in desired locations. Routing is then performed to connect the standard cells with each other and with other circuits on the chip. The conductive paths in each standard cell may incur parasitic effect due to undesirable layout in the standard cell. In advanced semiconductor technology, when millions of standard cells are integrated into a digital circuit, the effective parasitic effect caused by the huge number of standard cells may greatly degrade the speed and the power consumption of the digital circuit.